The present application relates to double-diffused MOS or “DMOS” power devices, and particularly to DMOS transistors which provide lateral carrier flow between their source/body regions and their drain regions, all of which have been formed along the walls of trenches that have been etched into the surface of a semiconductor wafer.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
DMOS transistors have become the dominant transistor type for solid-state power switching at voltages below about 500 volts. One innovation that has led to this dominance was the development of the trench MOSFET described in U.S. Pat. Nos. 4,767,722 and 5,034,785, both hereby incorporated by reference. Trench DMOS transistors or “TrenchFETs” operate in much the same fashion as conventional lateral or conventional vertical DMOS transistors. In a basic n-channel DMOS transistor, a heavily doped source region is separated from the drain region by a relatively narrow p-type body region. The source region is usually formed by introducing n-type dopant atoms along the same edge that was earlier used to introduce the p-type body dopant atoms. A gate region, which is most often doped polycrystalline silicon (“polysilicon),” is capacitively coupled to the body region. A sufficiently positive voltage on the gate with respect to the source inverts the normally p-type surface of the body region, thereby forming an n-type “channel” which allows n-type carriers (carrier electrons) to flow from the source region to the drain region of the device. The drain electrode may be formed on the same surface as the source/body electrode, or it may be formed on the opposite surface of the wafer.
Manufacturers of MOS-gated devices such as DMOS transistors have used a variety of methods to reduce the specific on-resistance of their products. The specific on-resistance, which is the product of the on-resistance of a device multiplied by its surface area, is one figure of merit often used as a basis for comparing device performance. The device with the lowest specific on-resistance for a given voltage has the most efficient use of surface area. The main device structures that have been used to manufacture commercially available DMOS transistors include lateral DMOS, vertical DMOS, and trench DMOS, all of which are shown in FIGS. 2A-2C respectively.
A fourth type of DMOS transistor, known as a “Super 3D MOSFET,” has been proposed for further reducing device size, particularly for devices operating at relatively low voltages. See J. Sakakibara, N. Suzuki, and H. Yamaguchi, “Break-through of the Si limit under 300V breakdown voltage with new concept power device: Super 3D MOSFET,” ISPSD, 2002, pp. 233-236; and H. Yamaguchi, Y. Urakami and J. Sakakibara, “Break-through of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage,” Proceedings of the 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Jun. 4-8, 2006. Both of these articles are hereby incorporated by reference.
A drawing of the Super 3D MOSFET is shown in FIG. 2D. Note that the predominant direction of current flow is lateral: carriers travel in an approximately horizontal plane. Thus a single horizontal slice through the device would include an operative DMOS transistor. The downwardly extended device can be thought of as a number of such operative transistors, downwardly stacked to give a very large total channel cross-section. While the concept of the Super 3D MOSFET is an extension of a trench MOSFET to three dimensions, the sequence of semiconductor processing steps that can be used for their manufacture is difficult to optimize.